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Timing Diagrams
6
Figure 6-1 on page 52 through Figure 6-57 on page 104 show the backend timing diagrams for different core
operations. The timing diagrams are taken directly from core simulations. Table 6-1 summarizes the timing waveforms
included in this handbook. Should additional waveforms be required, customers are encouraged to run simulations of the
core. These can be done with the free, downloadable Evaluation version of the core.
Table 6-1 · Example Waveforms
Description
Single-cycle read and write
Burst transfer at maximum transfer rate
Burst transfer with a slow PCI Master
Burst transfer with a slow backend
FIFO recovery operation
Byte-controlled transfers
64-bit burst transfer
Slow read transfers
Backend-terminated (BUSY) cycle at transfer start
Backend-terminated (ERROR) cycle at transfer start
Backend-terminated (BUSY) cycle during data burst
PCI configuration cycle
PCI interrupt generation
Simple DMA transfer
DMA cycle with a FIFO backend
STOP Master assertion during data burst
Figure(s)
6-1 to 6-3
6-4 to 6-6
6-7 to 6-9
6-10 to 6-13
6-14 to 6-15
6-16 to 6-18
6-19 to 6-21
6-22 to 6-23
6-24 to 6-25
6-26
6-27 to 6-29
6-30 to 6-31
6-32
6-33 to 6-37
6-38
6-39 to 6-42
RD_BUSY_MASTER and WR_BUSY_MASTER operation 6-43 to 6-44
STALL_MASTER operation
DMA register access from the backend
DMA direct transfers
Hot-swap insertion and extraction
6-45 to 6-48
6-49 to 6-53
6-54 to 6-55
6-56 to 6-57
The figures typically show three sets of waveforms for each transfer type: one write and two read cycles. The read
transfer is shown with a nonpipelined backend (RD_SYNC = 0) and a pipelined backend (RD_SYNC = 1). The
waveforms show 32-bit operation; 64-bit operation is identical to 32-bit operation. A single set of waveforms is shown
illustrating the 64-bit burst operation.
v4.0
51
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